Analog circuit design using graded-channel SOI nMOSFETs
(2001) 14th Symposium on Integrated Circuits and System Design (SBCCI′2001) — Location: Brazilia (Brazil) (30.August.2001)
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- Abstract
- An extended study of analog circuit design using Graded-Channel Silicon-On-Insulator MOSFETs in comparison to conventional fully-depleted transistors is performed. Performances of single-transistor operational transconductance amplifier implemented using Graded-Channel (GC) and conventional fully-depleted SOI nMOSFETs are compared. Improvements of the DC gain and unity-gain frequency resulting from the extremely reduced output conductance and the increased transconductance in the GC devices are discussed, based on experimental results, establishing design guidelines in order to aim at GC micropower or wide bandwidth OTAs. Two-dimensional simulations are used to analyze the intrinsic-gate capacitances in linear and saturation regions, establishing that GC transistors present almost the same capacitive amount than the conventional fully-depleted transistors in a typical analog range of operation.
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Citations
Pavanello, M. A., Martino, J. A., & Flandre, D. (2001). Analog circuit design using graded-channel SOI nMOSFETs. Proceedings of the 14th Symposium on Integrated Circuits and System Design (SBCCI′2001), 130-135. https://hdl.handle.net/2078.5/253168