Digital substrate noise reduction by low-power circuit operation and SOI technology
(2008) 7e journées d’étude Faible Tension Faible Consommation - FTFC 2008 — Location: Louvain-la-Neuve, Belgium (26.May.2008)
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- Abstract
- Progress of integrated circuit technology allows integration of analog and digital circuits on the same chip. This co-integration yields higher performances and reliability, while reducing power consumption, but also raises new challenges for circuit designers. The substrate noise generated by the switching digital part has detrimental effects on the analog part. In this contribution, a wide-band characterization of the so-called “digital substrate noise” is realized, in bulk and in SOI technology. The impact of low-power circuit operation mode on the digital substrate noise is investigated. A comparison of bulk and SOI technology with regard to the digital substrate noise level is also realized.
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Roda Neve, C., Bol, D., Ambroise, R., Flandre, D., & Raskin, J.-P. (2008). Digital substrate noise reduction by low-power circuit operation and SOI technology. Proceedings des 7e journées d’étude Faible Tension Faible Consommation, FTFC 2008, 23-28. https://hdl.handle.net/2078.5/253161