Asymmetric Self-Cascode Configuration to Improve the Analog Performance of SOI nMOS Transistors
(2011) IEEE International SOI Conference (SOI 2011) — Location: Tempe (USA) (3.October.2011)
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- Authors
- Abstract
- A recent work showed that gD of long-channel self-cascode transistors can be further reduced by replacing M2 with a transistor with intrinsic concentration in the channel. In order to extend this proposal to more recent technologies, the current work presents an analysis of short-channel asymmetric self-cascode transistors implemented using a multi-threshold voltage commercial process. Numerical simulations were also performed aiming to extend the study, searching for the optimal doping concentration and length for M1 and M2.
- Affiliations
Centro Universitário da FEI Department of Electrical Engineering
Citations
De Souza, M., Flandre, D., & Pavanello, M. A. (2011). Asymmetric Self-Cascode Configuration to Improve the Analog Performance of SOI nMOS Transistors. Proceedings of the IEEE International SOI Conference (SOI 2011), 1-2. https://doi.org/10.1109/SOI.2011.6081716