Modeling of the small-signal equivalent circuit of SOI FinFETs through SPICE simulations is presented. A compact model implemented in Verilog-A predicts well the DC characteristics of RF SOI FinFETs and allows the extraction of the intrinsic conductance, transconductance and capacitances at any selected operating point. The intrinsic small-signal equivalent circuit composed of those extracted lumped elements is used in SPICE simulator. This paper compares the parameters extracted from both DC and wideband S-parameter methods.
Alvarado, J., Tinoco, J. C., Kilchytska, V., Flandre, D., Raskin, J.-P., Cerdeira, A., & Contreras, E. (2012). Compact small-signal model for RF FinFETs. Proceedings of the 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012), 1-4. https://doi.org/10.1109/ICCDCS.2012.6188936