Low-Power Half-Rate Dual-Loop Clock-Recovery System in 28-nm FDSOI
(2018) 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS 2018) — Location: Puerto Vallarte (Mexico) (25.February.2018)
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- Abstract
- In this paper, a new dual-loop half-rate clock recovery is proposed for chip-to-chip communications. The halfrate topology allows for reducing the speed requirements of the blocks that constitute the clock-recovery system to achieve the required data-rate. The proposed topology is formed by a frequency-locked loop (FLL) active at startup for coarse PVT compensation and a phase-locked loop (PLL) taking over after startup to provide phase alignment between the clock and the data. The PLL uses a multi-level bang-bang phase detector for low-power. The proposed clock recovery circuit is designed for a 5-Gb/s data rate in a 28-nm FDSOI CMOS technology with two supply voltages (1 and 1.8V). It reaches an average power consumption of 1.43 mW under PLL operation.
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Citations
Gimeno Gasca, C., Flandre, D., & Bol, D. (2018). Low-Power Half-Rate Dual-Loop Clock-Recovery System in 28-nm FDSOI. 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS 2018), Puerto Vallarte (Mexico). https://hdl.handle.net/2078.5/253131