Ultra-low-power high-noise-margin logic with undoped FD SOI devices
(2009) 2009 IEEE International SOI Conference — Location: Foster City, CA, USA (5.October.2009)
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- Authors
Legat, Jean-Didier 
- Abstract
- Undoped devices in FD SOI technology provides improved switching speed to ULP logic, while keeping ultra-low leakage. Measurement results in 0.15 mu m FD SOI technology show that it can be used to build 500 kHz digital circuits for sensing applications, with 0.95 V noise margins at 1.5 V thanks to the hysteresis property of ULP logic. The record mean leakage current is 86 fA per gate, which enables digital circuits with 100 pW-range stand-by power, without the need for power-gating technique nor subthreshold operation. Additionally, the proposed FD SOI undoped ULP inverters can be used to build ultra-low-leakage 10 T or 12 T SRAM cells with the same architecture as proposed for bulk technology in, with reduced static current (~100 fA) and more compact layout.
- Affiliations
Citations
Bol, D., Legat, J.-D., De Vos, J., & Flandre, D. (2009). Ultra-low-power high-noise-margin logic with undoped FD SOI devices. 2009 IEEE International SOI Conference, 97-98. https://doi.org/10.1109/SOI.2009.5318760