Thin Film Fully-Depleted SOI Four-Gate Transistors
(2006) 2nd Workshop of the Thematic-Network-on-Silicon-on-Insulator-Technology-Devices-and-Circuits (EUROSOI 06) — Location: Grenoble (8.March.2006)
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- Authors
- Abstract
- The fully-depleted version of the SOI four-gate transistor (G4-FET) is introduced and its characteristics are systematically investigated. It is shown that the thinning-down of the silicon film promotes vertical coupling between the front and the back gates while mitigating the horizontal coupling between the lateral gates. As a consequence the direct influence of the lateral junction-gates on the body potential distribution is reduced. However, by biasing the back interface in inversion the junction-gates can indirectly modulate the body potential. This provides a very efficient control of the front-channel conduction parameters - such as threshold voltage, subthreshold swing and transconductance - by the junction-gates regardless the device width. The experimental results are clarified by 3-D device simulations and analytical modelling.
- Affiliations
Institut de Microélectronique, Electromagnétisme et Photonique (IMEP) The University of Tennessee ECE Department
Citations
Akarvardar, K., Cristoloveanu, S., Bawedin, M., Gentil, P., Blalock, B. J., & Flandre, D. (2006). Thin Film Fully-Depleted SOI Four-Gate Transistors. Solid-State Electronics, 51(2), 278-284. https://doi.org/10.1016/j.sse.2007.01.013 (Original work published 2006)