Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures
(2015) 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro) — Location: Salvador (31.August.2015)
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UseofBackGateBiastoEnhancetheAnalogPerformanceofPlanarFDandUTBBSOITransistors-BasedSelf-CascodeStructures.pdf
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- Abstract
- This paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.
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Citations
Dorai, R. T., Flandre, D., Trevisoli, R., de Souza, M., & Pavanelo, M. A. (2015). Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures. Proceedings of SBMicro 2015. Published. 2015 30th Symposium on Microelectronics Technology and Devices (SBMicro), Salvador. https://doi.org/10.1109/SBMicro.2015.7298134