The rising integration level of mixed-signal integrated circuits raises new issues for designers. Substrate noise generated by the switching digital part has a detrimental impact on the performance of the analog/RF parts. This contribution introduces simulation and experimental characterization of so-called "digital substrate noise" on a 0.13- mu m SOI CMOS process with high resistivity (HR) substrate. To the authors knowledge, it is the first time that that it is addressed in SOI technology at circuit level.
Bol, D., Ambroise, R., Roda Neve, C., Raskin, J.-P., & Flandre, D. (2007). Wide-band simulation and characterization of digital substrate noise in SOI technology. Proccedings 2007 IEEE International SOI Conference, 133-134. https://hdl.handle.net/2078.5/253064