The Detrimental Impact of Negative Celsius Temperature on Ultra-Low-Voltage CMOS Logic
(2010) ESSCIRC 2010, Euroean Solid-State Circuits Conference — Location: Valencia (Spain) (13.September.2010)
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- Authors
Legat, Jean-Didier 
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Bol, D., Hocquet, C., Flandre, D., & Legat, J.-D. (2010). The Detrimental Impact of Negative Celsius Temperature on Ultra-Low-Voltage CMOS Logic. Proceedings of the ESSCIRC 2010, p. 522 - 525. https://hdl.handle.net/2078.5/253056