Analysis of harmonic distorsion in graded-channel SOI MOSFETS at high temperatures
(2004) Nineteenth International Symposium on Microelectronics Technology and Devices (SBMICRO 2004) — Location: Porto de Galinhas Beach (Brazil) (7.September.2004)
Files
No attached file found for this publication.
Details
- Authors
- Abstract
- An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature up to 423 K. The total harmonic distortion and third order harmonic distortion have been adopted as figures of merit. It is shown that the total harmonic distortion decreases as the length of the lightly doped region is increased in GC transistors, due to reduction of the effective voltage amplitude that is applied on the conventionally doped part of the channel. On the other hand, the third order harmonic distortion increases with the length of lightly doped region. The temperature increase tends to reduce the total harmonic distortion and the third order harmonic.
- Affiliations
Citations
Pavanello, M. A., Cerdeira, A., Martino, J. A., Aleman, M. A., & Flandre, D. (2004). Analysis of harmonic distorsion in graded-channel SOI MOSFETS at high temperatures. In Santos E.J.P., Ribas R.P., Swart J. Eds. (ed.), Proceedings of the Nineteenth International Symposium on Microelectronics Technology and Devices (SBMICRO 2004) (pp. 39-44). https://hdl.handle.net/2078.5/253008