Analysis and modelling of Temperature Effect on DIBL in UTBB FD SOI MOSFETs

Pereira, Arianne Soares do Nascimento;de Streel, Guerric;Planes, N.;Haond, M.;Kilchytska, Valeriya;et.al.
(2016) 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2016) — Location: Vienne (Austria) (25.January.2016)

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Authors
  • Pereira, Arianne Soares do NascimentoUCLouvain
    Author
  • de Streel, GuerricUCLouvain
    Author
  • Planes, N.STMicroelectronics, Crolle/France
    Author
  • Haond, M.STMicroelectronics, Crolle/France
    Author
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Abstract
The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150ºC, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrarily to MASTAR prediction, experiments reveal DIBL increase with temperature. SPICE simulations, with model UTSOI DK2.4, adhere to experimental trends. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the most accurate found, Fasarakis’ model presents some inaccuracy for upsized gate lengths frequently used in ULV (ultralow-voltage) applications. This model was improved in this work, by introducing a temperature-dependent inversion charge at threshold. The improved model showed very good agreement with experimental data, with high gain of precision (35%) for the addressed gate lengths.
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Citations

Pereira, A. S. d. N., de Streel, G., Planes, N., Haond, M., Giacomini, R., Flandre, D., & Kilchytska, V. (2016). Analysis and modelling of Temperature Effect on DIBL in UTBB FD SOI MOSFETs. Proceedings de la conférence EUROSOI-ULIS 2016, 116-119. https://doi.org/10.1109/ULIS.2016.7440066