Comparison of 0.25 µm Bulk, PD and FD SOI CMOS implementations of a Low-Voltage Low-Power Programmable DLL for Linear Delay Generation
(2000) 2000 IEEE International SOI Conference — Location: Wakefield, MA (USA) (2.October.2000)
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- Abstract
- This paper describes the SOI implementation of a low-voltage low-power programmable delay locked loop (DLL) for linear delay generation in graphics display applications. In order to achieve the best linearity performance, a new scale structure with programmable delay stages is introduced. Since a programmable stage increases the complexity and thus the minimum achievable delay, a high performance technology is required to implement the target specifications. Simulation results in 0.25 μm bulk, partially-depleted (PD) and fully-depleted (FD) SOI CMOS are compared and experimental results are reported for the most promising FD process
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Citations
Delatte, P., Brodéoux, V., Lorent, Ph., & Flandre, D. (2000). Comparison of 0.25 µm Bulk, PD and FD SOI CMOS implementations of a Low-Voltage Low-Power Programmable DLL for Linear Delay Generation. Proceedings of the 2000 IEEE International SOI Conference, 92-93. https://hdl.handle.net/2078.5/252949