Impact of Asymmetric Channel Configuration on the Linearity of Double-Gate SOI MOSFETs
(2006) 6th International Caribbean Conference on Devices, Circuits and Systems — Location: Mexico (26.April.2006)
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- Abstract
- In this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and gate-all-around architecture, operating as an amplifier, is studied in terms of lightly doped region length. The total harmonic distortion and third-order harmonic distortion are used as figures of merit. The results are compared with single-gate transistors with similar channel configuration. It is demonstrated that double-gate GC transistors at the same operation region and with similar channel configuration can present up to 20 dB less total harmonic distortion while presenting small third-order harmonic distortion. Considering similar bias voltage, the alternate component of the input sinusoidal signal of GC double-gate devices can be increased by about 200 mV to provide similar third-order harmonic distortion maintaining similar improvements of 20 dB on the total harmonic distortion
- Affiliations
Centro Universitário da FEI, São Bernardo do Campo, SP, Brazil Departamento de Engenharia Eletrica CINVESTAV Department of Electrical Engineering Centro Universitário da FEI, São Bernardo do Campo, SP, Brazil Department of Electrical Engineering
Citations
Pavanello, M. A., Cerdeira, A., Martino, J. A., Raskin, J.-P., & Flandre, D. (2006). Impact of Asymmetric Channel Configuration on the Linearity of Double-Gate SOI MOSFETs. Proceedings of the 6th International Caribbean Conference on Devices, Circuits and Systems, 187-192. https://hdl.handle.net/2078.5/252945