Building ultra-low-power low-frequency digital circuits with high-speed devices

Bol, David;Legat, Jean-Didier;Ambroise, Renaud;Flandre, Denis
(2007) 2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS ’07) — Location: Marrakech, Morocco (11.December.2007)

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Leakage current is the main source of power dissipation in low-frequency digital circuits implemented in deep submicron processes. This contribution introduces a novel active-mode leakage reduction technique for ultra-low-power (ULP) low-frequency applications. It is based on the ULP CMOS logic style achieving negative-V/sub GS/ self-biasing ULP logic gates have static current reduced by several orders of magnitude. For a commercial 0.13- mu m technology, power consumption of ULP gates at low frequencies is lower than standard CMOS counterparts even considering high-V/sub T/ devices, subthreshold operation and reverse body biasing. ULP gates are shown to be very stable against process, voltage and temperature variations.
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Bol, D., Legat, J.-D., Ambroise, R., & Flandre, D. (2007). Building ultra-low-power low-frequency digital circuits with high-speed devices. 2007 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS ’07), p. 1404-1407. https://hdl.handle.net/2078.5/252942