Interests and Limitations of Technology Scaling for Subthreshold Logic
(2009) IEEE Transactions on Very Large Scale Integration (VLSI) Systems — Vol. 17, n° 10, p. 1508-1519 (2009)
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- Authors
Legat, Jean-Didier 
- Abstract
- Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mu m to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mu m node. Up-sizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.
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Citations
Bol, D., Ambroise, R., Flandre, D., & Legat, J.-D. (2009). Interests and Limitations of Technology Scaling for Subthreshold Logic. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(10), 1508-1519. https://doi.org/10.1109/TVLSI.2008.2005413 (Original work published 2009)