Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs
(2011) Solid-State Electronics — Vol. 59, n° 1, p. 50-61 (2011)
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- Abstract
- This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, Gmmax, and analog figures of merit, such as transconductance over drain current ratio, Gm/ID, output conductance, GD, Early voltage, VEA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data obtained on FinFETs. We show that the presence of negative charges at the gate edges while degrading the subthreshold behavior and analog figures of merit (especially for long-channel devices) can result in apparent improved control of short-channel effects and higher Gmmax. The origin of such twofold impact of negative charges at the gate edges on the device behavior is also analyzed by 2-D device simulations and a simplified two-transistors model.
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Kilchytska, V., Alvarado, J., Collaert, N., Rooyackers, R., Put, S., Simoen, E., Claeys, C., & Flandre, D. (2011). Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs. Solid-State Electronics, 59(1), 50-61. https://doi.org/10.1016/j.sse.2011.01.008 (Original work published 2011)