Hybrid full-adder cell in 0.13 µm PD SOI CMOS for low-voltage low-power applications
(2005) EUROSOI 2005 - First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits — Location: Granada, Spain (19.January.2005)
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Legat, Jean-Didier 
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Hassoune, I., Legat, J.-D., & Flandre, D. (2005). Hybrid full-adder cell in 0.13 µm PD SOI CMOS for low-voltage low-power applications. Proceedings of the First Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits, p. 123-124. https://hdl.handle.net/2078.5/252810