Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors
(2012) 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012) — Location: Playa del Carmen (14.March.2012)
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- Abstract
- This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric self-cascode.
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De Souza, M., Pavanello, M. A., & Flandre, D. (2012). Analog performance of asymmetric self-cascode p-channel fully depleted SOI transistors. Proceedings of the 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2012), 1-4. https://doi.org/10.1109/ICCDCS.2012.6188932