Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology
(1997) 22nd European Solid-State Circuits Conference (ESSCIRC 1996) — Location: Neuchatel (Suisse) (17.September.1996)
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- Abstract
- A systematic study of the gain-boosted regulated-cascode operational transconductance amplifier (OTA) CMOS stage is presented. Symbolic analysis is used first to describe the pole-zero behaviour and second to propose design criteria for optimal settling time. A synthesis procedure based on the “gm/ID” methodology is considered further on for quick optimization of the architecture based on the dc open-loop gain, transition frequency, and settling time specifications. Practical design cases are finally discussed.
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Flandre, D., Viviani, A., Eggermont, J.-P., Gentinne, B., & Jespers, P. (1997). Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology. Proceedings of the 22nd European Solid-State Circuits Conference (ESSCIRC 1996). 22nd European Solid-State Circuits Conference (ESSCIRC 1996), Neuchatel (Suisse). https://hdl.handle.net/2078.5/252798