Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems
(2011) Proceedings de FTFC 2011, Faible Tension Faible Consommation — Location: Marrakech (Maroc) (31.May.2011)
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- Abstract
- In this paper, we describe applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS mixed analog-digital microsystems without compromising the functional performance. The technique is based on a pair of source-connected n- and p-MOS transistors, automatically biasing the stand-by gate-to-source voltage of the nMOSFET at a negative voltage and that of the pMOSFET at a positive level, thereby pushing the off current towards its physical limits. Playing with gate and drain connections, we have created a family of ULP basic blocks: a 2-terminal diode, a 3-terminal transistor and a voltage follower. Using these blocks, we have developed a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high speed performance, highly-efficient power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.
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Citations
Flandre, D., Bulteel, O., Gosset, G., Rue, B., & Bol, D. (2011). Disruptive ultra-low-leakage design techniques for ultra-low-power mixed-signal microsystems. Proceedings de FTFC 2011, Faible Tension Faible Consommation, Marrakech (Maroc). https://hdl.handle.net/2078.5/252755