Analysis and Optimization for Dynamic Read Stability in 28nm SRAM Bitcells
(2015) IEEE International Conference on Circuits and Systems (ISCAS 2015) — Location: Lisbon (Portugal) (24.May.2015)
Files
AnalysisandOptimizationforDynamicReadStabilityin28nmSRAMBitcells.pdf
Restricted Access - Adobe PDF
- 516.07 KB
Details
- Authors
- Abstract
- The importance of the dynamic analysis for SRAM operation increases as a result of shrinking access cycle time, voltage scaling and increased process variations. In this paper, quantitative study of the dynamic read noise margin (DNM) is introduced showing the evolution from the static read noise margin (SNM) to DNM through cumulative dynamic effects in 28nm FDSOI. The impact of parasitic capacitances on the DNM is further analyzed. Finally, we show that by sizing for a 150-mV DNM instead of a 150-mV SNM and by inserting two 0.5fF extra caps in the bitcell allows reducing the pull-down NMOS width by a factor 3.5×.
- Affiliations
Citations
Taha Elthakeb Naguib Youssef, A., Haine, T., Flandre, D., Ismail, Y., Elhamid, H. A., & Bol, D. (2015). Analysis and Optimization for Dynamic Read Stability in 28nm SRAM Bitcells. Proceedings of ISCAS 2015, 14141417. https://doi.org/10.1109/ISCAS.2015.7168908