Ultra-low power flip-flops for MTCMOS circuits
(2005) IEEE International Symposium on Circuits and System (ISCAS 2005) — Location: Kobe, Japan (23.May.2005)
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- Abstract
- This paper deals with new MTCMOS flip-flop architectures with high speed performance in active mode and ultra-low power dissipation in sleep mode. The use of new ultra-low leakage latch structure allows us to memorize the flip-flop state even during sleep mode and to strongly reduce the leakage in comparison with previous solutions.
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Citations
Levacq, D., Dessard, V., & Flandre, D. (2005). Ultra-low power flip-flops for MTCMOS circuits. Proceedings of the IEEE International Symposium on Circuits and System (ISCAS 2005), 4681-4684. https://doi.org/10.1109/ISCAS.2005.1465677