Comparison of ultra-low-power and static CMOS full adders in 0.15 mu m FD SOI CMOS
(2009) 2009 IEEE International SOI Conference — Location: Foster City, CA, USA (5.October.2009)
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- Abstract
- Ultra-low-power and static CMOS full adders are implemented in a 0.15 mu m FD SOI CMOS technology with 1.5 V supply. The power consumption of ultra-low-power full adder is shown to be half that of static CMOS. These results are confirmed by both measurements and SPICE simulations in different corners of operation.
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Citations
Kamel, D., Standaert, F.-X., Bol, D., & Flandre, D. (2009). Comparison of ultra-low-power and static CMOS full adders in 0.15 mu m FD SOI CMOS. 2009 IEEE International SOI Conference, 2 pp. https://doi.org/10.1109/SOI.2009.5318751