A 65nm 1V to 0.5V Linear Regulator with Ultra Low Quiescent Current for Mixed-Signal ULV SoCs

de Streel, Guerric;De Vos, Julien;Flandre, Denis;Bol, David
(2014) 2014 IEEE FTFC Conference — Location: Monaco (4.May.2014)

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Abstract
A linear regulator for point of load power delivery with 280nA quiescent current and 0:008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0:5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0:5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.
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de Streel, G., De Vos, J., Flandre, D., & Bol, D. (2014). A 65nm 1V to 0.5V Linear Regulator with Ultra Low Quiescent Current for Mixed-Signal ULV SoCs. 2014 IEEE FTFC Conference, Monaco. https://doi.org/10.1109/FTFC.2014.6828597