A Novel CMOS Memory Cell Architecture for Ultra-Low Power Applications Operating up to 280°C
(2003) ECS 11th International Symposium on SOI Technology and Devices — Location: Paris (France) (22.April.2003)
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- Abstract
- A CMOS memory cell is demonstrated. It achieves a strong reduction of the static and dynamic power consumptions by using transistors in very weak inversion regimes. It is intended for low supply voltages applications and is resistant to high temperature conditions. The cell has been successfully implemented on a fully depleted SOI CMOS process.
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Citations
Levacq, D., Dessard, V., & Flandre, D. (2003). A Novel CMOS Memory Cell Architecture for Ultra-Low Power Applications Operating up to 280°C. Proceedings of the ECS 11th International Symposium on SOI Technology and Devices, 249-254. https://hdl.handle.net/2078.5/252577