Dynamic differential self-timed logic families for robust and low-power security ICs
(2007) Integration : the V L S I journal — Vol. 40, n° 3, p. 355-364 (2007)
Files
pdfdocument.pdf
Restricted Access - Adobe PDF
- 514.83 KB
Details
- Authors
Legat, Jean-Didier 
- Abstract
- This paper describes two new dynamic differential self-timed logic families that can be used either to implement low-power security components or low-power high-speed self-timed circuits. Electrical simulations in 0.13 mu m partially depleted (PD) SOI CMOS under a V-dd of 1.2 V have shown that the substitution box (S-box), a module of the Khazad cipher algorithm, implemented with the improved feedback low swing current mode logic (IFLSCML) features a power consumption standard deviation almost five times smaller than that of the self-timed DDCVSL one, while consuming 37% less. On the other hand, the 8b CLA implemented with dynamic differential swing limited logic (DDSLL) features a power delay product about 19% lower than that of its counterpart implemented with self-timed DDCVSL. (c) 2006 Elsevier B.V. All rights reserved.
- Affiliations
Citations
Hassoune, I., Macé, F., Flandre, D., & Legat, J.-D. (2007). Dynamic differential self-timed logic families for robust and low-power security ICs. Integration : the V L S I journal, 40(3), 355-364. https://doi.org/10.1016/j.vlsi.2006.04.001 (Original work published 2007)