Compensation of Total Ionizing Dose Effects in ULV SoCs Through Adaptive Voltage Scaling

De Vos, Julien;Kilchytska, Valeriya;Flandre, Denis;Bol, David
(2014) 2014 IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S) — Location: San Francisco (USA) (6.October.2014)

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Abstract
Total ionizing dose (TID) jeopardizes the operation of ULV circuits by shifting the threshold voltage of the devices. Measurements on a 65nm SoC show that it modifies the output of an on-chip 4-T voltage reference by 3.5% and the gate delay at ULV by 17%. This harms the timing closure of ULV digital systems based a conventional power management architecture generating constant clock frequency and supply voltage. We show by experimental measurements that the use of an on-chip adaptive voltage scaling system efficiently cancels these effects of TID for robust timing closure at ULV.
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De Vos, J., Kilchytska, V., Flandre, D., & Bol, D. (2014). Compensation of Total Ionizing Dose Effects in ULV SoCs Through Adaptive Voltage Scaling. 2014 IEEE SOI-3D Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco (USA). https://doi.org/10.1109/S3S.2014.7028238