Compact diamond MOSFET model accounting for PAMDLE applicable down 150nm node

Gimenez, Salvador Pinillos;Davini, Enrico;Peruzzi, Vinicius;Renaux, Christian;Flandre, Denis
(2014) Electronics Letters — Vol. 50, n° 22, p. 1618-1620 (2014)

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Authors
  • Gimenez, Salvador PinillosCentro Universitario da FEI, Brazil
    Author
  • Davini, EnricoCentro Universitario da FEI, Brazil
    Author
  • Peruzzi, ViniciusCentro Universitario da FEI, Brazil
    Author
  • Renaux, ChristianUCLouvain
    Author
  • Flandre, DenisUCLouvain
    Author
Abstract
The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal–oxide semiconductor field-effect transistors (MOSFETs) implemented with diamond layout style (hexagonal gate geometry) are quantified, thanks to the longitudinal corner effect and parallel association of MOSFETs with different channel lengths effect contributions. Futhermore, an accurate analytical drain current model for planar diamond SOI MOSFET for micrometre scale effective channel lengths is proposed and validated. The concept is then extended by 3D simulations for the 150 nm node fully-depleted SOI n-channel MOSFETs.
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Gimenez, S. P., Davini, E., Peruzzi, V., Renaux, C., & Flandre, D. (2014). Compact diamond MOSFET model accounting for PAMDLE applicable down 150nm node. Electronics Letters, 50(22), 1618-1620. https://doi.org/10.1049/el.2014.1229 (Original work published 2014)