Investigation of low-power low-voltage circuit techniques for a hybrid full-adder cell
(2004) 14th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2004) — Location: Santorini (Greece) (15.September.2004)
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- Authors
Legat, Jean-Didier 
- Abstract
- A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL_PT) and its counterpart in conventional CMOS logic, was carried out in a 0.13mum PD (partially depleted) SOI CMOS for a supply voltage of 1.2V and a threshold voltage of 0.28V. Moreover, MTCMOS (multi-threshold) circuit technique was applied on the proposed full-adder to achieve a trade-off between Ultra-Low power and high performance design. Design with DTMOS (dynamic threshold) devices was also investigated with two threshold voltage values (0.28V and 0.4V) and V-dd = 0.6V.
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Citations
Hassoune, I., Legat, J.-D., Neve, A., & Flandre, D. (2004). Investigation of low-power low-voltage circuit techniques for a hybrid full-adder cell. Lecture Notes in Computer Science, 3254, 189-197. https://hdl.handle.net/2078.5/252482 (Original work published 2004)