Impact of layout style and parasitic capacitances in full adder
(2008) 2008 IEEE International SOI Conference — Location: New Paltz, NY, USA (6.October.2008)
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- Abstract
- This paper presents the impact of varying both the architecture and the technology on the performance of the full adder. A 10% reduction in total power and 15.2% reduction in delay are gained by changing the architecture. While an average power reduction of 15.5% and 14.1% reduction in average delay are gained by using SOI layout and junction capacitances instead of bulk.
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Kamel, D., Bol, D., & Flandre, D. (2008). Impact of layout style and parasitic capacitances in full adder. Proceedings of the 2008 IEEE International SOI Conference, 97-98. https://doi.org/10.1109/SOI.2008.4656312