An 8-T ULV SRAM macro in 28nm FDSOI with 7.4 pW/bit retention power and back-biased-scalable speed/energy trade-off

Haine, Thomas;Flandre, Denis;Bol, David
(2018) IEEE S3S Conference — Location: San Francisco (USA) (15.October.2018)

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Abstract
In this paper, we propose an ultra-low-voltage SRAM macro in 28nm FDSOI based on an 8-T ULP bitcell. Data retention in the proposed bitcell is obtained with two CMOS negative-differential resistance structures, which allow for using only low-Vt transistors for density and speed without prohibitive leakage. The bitcell was sized to reach low failure rate for 32-kB macro with a gradient-based importance sampling methodology. Thanks to the exclusive use of low-Vt transistors, adaptive back biasing allows for compensating PVT variations as well as scaling the power/performance trade-off. At 0.55V, the proposed SRAM can operate at up to 200 MHz and reaches an average access energy of 20.4 fJ/bit. In sleep mode with data retention, the leakage power goes down to 7.4 pW/bit.
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Haine, T., Flandre, D., & Bol, D. (2018). An 8-T ULV SRAM macro in 28nm FDSOI with 7.4 pW/bit retention power and back-biased-scalable speed/energy trade-off. IEEE S3S Conference, San Francisco (USA). https://hdl.handle.net/2078.5/252465