High-temperature characterization of a PD SOI CMOS process with LDMOS and lateral bipolar structures
(1999) Conference HITEN 1999 — Location: Berlin (Germany) (4.July.1999)
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- Abstract
- High-temperature characterization of a 0.8 μm partially-depleted (PD) silicon-on-insulator (SOI) CMOS process is reported. The process is designed for mixed analog/digital/high-voltage applications. The measurements have been realized on n-MOSFETs, on lateral bipolar transistors and on LDMOS transistors and demonstrate the interest of the process under consideration.
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Citations
Adriaensen, S., Dessard, V., Delatte, P., Querol, J. R., Flandre, D., & Richter, S. (1999). High-temperature characterization of a PD SOI CMOS process with LDMOS and lateral bipolar structures. Proceedings of HITEN 1999, 79-82. https://doi.org/10.1109/HITEN.1999.827467