Power-Aware HEVC Compression Through Asymmetric JPEG XS Frame Buffer Compression
(2018) 25th IEEE International Conference on Image Processing (ICIP) — Location: Athens, Greece (7.October.2018)
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- Abstract
- With the emergence of UHD video, reference frame buffers (FBs) inside HEVC-like encoder and decoder chips have to sustain huge bandwidth. The power consumption due to the accesses to these off-chip memories accounts for a significant share of the codec's total consumption. This paper describes a JPEG XS-based frame buffer compression solution intended to decrease the FB's bandwidth, making HEVC more suitable for use in power-aware applications. As opposed to previous works, our solution compresses large picture areas (ranging from a CTU to a frame stripe) independently and is suitable for use in several data reuse strategies. According to experimental results, this work provides significant off-chip bandwidth and memory size reduction (DRR) at the cost of a slight rate increase. In particular, at low rates and if FBC is applied at HEVC encoder only, the DRR is as high as 83.3% with a <4% rate increase and <0.12dB quality drop on average.
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Willème, A., Macq, B., Descampe, A., & Gaël Rouvroy. (2018). Power-Aware HEVC Compression Through Asymmetric JPEG XS Frame Buffer Compression. 25th IEEE International Conference on Image Processing (ICIP), Athens, Greece.