Back-gate bias Effect on the MOSFET-C CMOS UTBB Performance by Circuit Simulations

Martínez, A.;Alvarado, J.;Kilchytska, Valeriya;Alcántara, S.;Flandre, Denis
(2019) 5th joint EUROSOI – ULIS 2019 Conference — Location: Grenoble (France) (April.2019)

Files

BackgatebiasEffectontheMOSFET-CCMOSUTBBPerformancebyCircuitSimulations.pdf
  • Open Access
  • Adobe PDF
  • 281.65 KB
Download

Details

Authors
  • Martínez, A.Benemérita Universidad Autónoma de Puebla, CIDS, Av. San Claudio y 18 Sur, Col. San Manuel, Ciudad Universitaria, CP 72570, P.O. Box 1067, Puebla, Pue., 7200, Mexico
    Author
  • Alvarado, J.Benemérita Universidad Autónoma de Puebla, CIDS, Av. San Claudio y 18 Sur, Col. San Manuel, Ciudad Universitaria, CP 72570, P.O. Box 1067, Puebla, Pue., 7200, Mexico
    Author
  • Kilchytska, ValeriyaUCLouvain
    Author
  • Alcántara, S.Benemérita Universidad Autónoma de Puebla, CIDS, Av. San Claudio y 18 Sur, Col. San Manuel, Ciudad Universitaria, CP 72570, P.O. Box 1067, Puebla, Pue., 7200, Mexico
    Author
  • Flandre, Denisorcid-logoUCLouvain
    Author
Abstract
This work investigates the on-resistance and harmonic distortion (HD) of Ultra-Thin Body and Buried Oxide (UTBB) fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFETs for a typical process (TT) working in the triode regime, of interest for MOSFET-C filter applications. Circuit simulations of the DC characteristics of n- and p-type MOSFETs in a large temperature range (-25ºC–150ºC) allow to identify the interest of the back-gate bias to compensate the shift of the on-resistance and 3rd - order HD with the temperature.
Affiliations

Citations

  • APA
  • Chicago
  • FWB

Martínez, A., Alvarado, J., Kilchytska, V., Alcántara, S., & Flandre, D. (2019). Back-gate bias Effect on the MOSFET-C CMOS UTBB Performance by Circuit Simulations. 5th joint EUROSOI – ULIS 2019 Conference, Grenoble (France). https://hdl.handle.net/2078.5/228387