Comparison of Digital Substrate Noise in SOI and Bulk Si CMOS Technologies
(2008) 7th Workshop on Low-Voltage Low Power Design — Location: Louvain-la-Neuve (Belgium) (26.May.2008)
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- Abstract
- Progress of integrated circuit technology allows integration of analog and digital circuits on the same chip. This co-integration yields higher performances and reliability, while reducing power consumption, but also raises new challenges for circuit designers. The substrate noise generated by the switching digital part has detrimental effects on the analog part. In this contribution, a wide-band characterization of the so-called “digital substrate noise” is realized, in bulk and in SOI technology. The impact of lowpower circuit operation mode on the digital substrate noise is investigated. A comparison of bulk and SOI technology with regard to the digital substrate noise level is also realized.
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Citations
Roda Neve, C., Bol, D., Ambroise, R., Flandre, D., & Raskin, J.-P. (2008). Comparison of Digital Substrate Noise in SOI and Bulk Si CMOS Technologies. 7th Workshop on Low-Voltage Low Power Design, Louvain-la-Neuve (Belgium). https://hdl.handle.net/2078.5/227952