Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors

Doria, R.T.;Trevisoli, R.;de Souza, Michelly;Pavanello, Marcelo Antonio;Flandre, Denis
(2017) 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) — Location: Burlingame, California (USA ) (10.October.2016)

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  • Doria, R.T.Centro universitario FEI, Sao Bernardo do Campo, Brazil
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  • Trevisoli, R.UCLouvain
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  • de Souza, MichellyUCLouvain
    Author
  • Pavanello, Marcelo AntonioUCLouvain
    Author
  • Flandre, DenisUCLouvain
    Author
Abstract
This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices.
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Doria, R. T., Trevisoli, R., de Souza, M., Pavanello, M. A., & Flandre, D. (2017). Use of back gate bias to improve the performance of n- and p-type UTBB transistors-based self-cascode structures applied to current mirrors. Proceedings of the 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). Published. 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, California (USA ). https://doi.org/10.1109/S3S.2016.7804387