Single Event Effects and Total Ionising Dose in 600V Si-on-SiC LDMOS Transistors for Rad-Hard Space Applications

Ben Ali, Khaled;Gammon, P.M.;Chan, C.W.;Li, F.;Kilchytska, Valeriya;et.al.

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SingleEventEffectsandTotalIonisingDoisein600VSi-on-SiCLDMOSTransistorsforRad-HardSpaceApplications.doc
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Authors
  • Ben Ali, KhaledUCLouvain
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  • Gammon, P.M.School of Engineering, University of Warwick, Coventry/UK
    author
  • Chan, C.W.School of Engineering, University of Warwick, Coventry/UK
    author
  • Li, F.School of Engineering, University of Warwick, Coventry/UK
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Abstract
This work presents a novel Si-on-SiC laterally-diffused (LD) MOSFET structure intended to provide high breakdown voltage of 600 V and be resistant for harsh-environment space applications. Single-event effects (SEE) and total ionizing dose (TID) are investigated for the first time in such device. Initially, the considered Si LDMOS structure on SiC suffers from single-event burnout (SEB) at a drain voltage > 175 V, i.e. much lower than the target. An optimized LDMOS structure with a heavily doped extended P+ buried region is proposed and shown to be SEB resistant at the target drain voltage of 600 V, even for a highly-energetic ion with a linear energy transfer (LET) of 90 MeV/mg/cm2. TID simulations indicate that the main concern is the charge build-up in the thick field oxide (FOX). FOX positive charge density beyond 1x1011 cm-2 causes the breakdown voltage to drop below 200 V. Different oxide types which feature low “net” positive charge build-up have to be considered to allow for higher TID hardness. The proposed Si/SiC structure with a p+ region was shown to be resistant to a combined SEE and TID (in case of limited positive charge build-up in FOX) as well as combined SEE and high-temperature (up to 573 K) environments. In comparison to the equivalent Silicon-on-Insulator (SOI) LDMOS, the Si/SiC LDMOS structure with p+ buried region features similar immunity to SEB but allows for higher TID hardness.
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