A low-power 5 GHz CMOS LC-VCO optimized for high-resistivity SOI substrates
(2005) 31st European Solid-State Circuits Conference — Location: Grenoble, France (12.September.2005)
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- Abstract
- This paper discusses the power saving of an LC-VCO designed on high-resistivity SOI substrates ( rho > 1000 Omega middot cm). It demonstrates the drastic improvement in the varactors and inductors quality factor on these substrates. It stresses on the importance of optimizing the tank inductor and the VCO for high-resistivity substrates. A 5GHz VCO designed in a 0.13 mu m partially depleted SOI CMOS confirms the low-power performance with a figure-of-merit greater than 190, placing this design at the top of the state-of-the-art.
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Delatte, P., Picun, G., Demeus, L., Simon, P., & Flandre, D. (2005). A low-power 5 GHz CMOS LC-VCO optimized for high-resistivity SOI substrates. In Fesquet, L.; Kaiser, A.; Cristoloveanu, S.; Brillouet, M.; (ed.), Proceedings of ESSCIRC 2005. 31st European Solid-State CircuitsConference (IEEE Cat. No. 05EX1088) (pp. 395-398). IEEE. https://doi.org/10.1109/ESSCIR.2005.1541643