Design of a branch-based carry-select adder IP portable in 0.25 mu m bulk and silicon-on-insulator CMOS technologies

Neve, Amaury;Flandre, Denis
(2002) SOC Design Methodologies. IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC′01) — Location: Montpellier (France)

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By reducing the parasitic node capacitances, the Branch-Based Logic design style can increase the performances of digital circuits. In order to benefit from the full potential of the design style and to be able to port it to different technologies, it is important to take into account the specific features of each technology. We investigate the case of three advanced 0.25 mu m CMOS technologies: bulk, Partially-depleted SOI and fully-depleted SOI. The design of a 16-bit carry-select branch-based adder IP is discussed. The branch-based adder shows lower power consumption compared to an implementation with conventional CMOS logic gates.
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Neve, A., & Flandre, D. (2002). Design of a branch-based carry-select adder IP portable in 0.25 mu m bulk and silicon-on-insulator CMOS technologies. In Robert, M.; Rouzeyre, B.; Piquet, C.; Flottes, M.-L.; (ed.), SOC Design Methodologies. IFIP TC10/WG10.5 Eleventh InternationalConference on Very Large Scale Integration of Systems-on-Chip(VLSI-SOC′01) (pp. 169-180). Kluwer academic publishers. https://hdl.handle.net/2078.5/222805