Ultra-low power flip-flops for MTCMOS circuits

Levacq, D.;Dessard, V.;Flandre, Denis
(2005) IEEE International Symposium on Circuits and Systems (ISCAS) — Location: Kobe, Japan (23.May.2005)

Files

No attached file found for this publication.

Details

Authors
Abstract
This paper deals with new MTCMOS flip-flop architectures with high speed performance in active mode and ultra-low power dissipation in sleep mode. The use of new ultra-low leakage latch structure allows us to memorize the flip-flop state even during sleep mode and to strongly reduce the leakage in comparison with previous solutions.
Affiliations

Citations

  • APA
  • Chicago
  • FWB

Levacq, D., Dessard, V., & Flandre, D. (2005). Ultra-low power flip-flops for MTCMOS circuits. proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat.No. 05CH37618), Vol. 5, p. 4681-4. https://hdl.handle.net/2078.5/221168