Analysis on the improved analog performance on double gate transistors by using the graded-channel architecture in a wide temperature range

Pavanello, M.A.;Martino, J.A.;Raskin, Jean-Pierre;Flandre, Denis
(2005) Solid-State Electronics, Elsevier Science, Pergamon — Vol. 49, n° 10, p. 1569-1575 (October) (2005)

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Pavanello, M. A., Martino, J. A., Raskin, J.-P., & Flandre, D. (2005). Analysis on the improved analog performance on double gate transistors by using the graded-channel architecture in a wide temperature range. Solid-State Electronics, Elsevier Science, Pergamon, 49(10), 1569-1575 (October). https://hdl.handle.net/2078.5/211373 (Original work published 2005)