Influence of device engineering on the analog and RF performances of SOI MOSFETs
(2003) IEEE Transactions on Electron Devices — Vol. 50, n° 3, p. 577-588 (2003)
Files
No attached file found for this publication.
Details
- Authors
- Abstract
- This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 mum. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices,,of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).
- Affiliations
Citations
Kilchytska, V., Flandre, D., Neve, A., Vancaillie, L., Levacq, D., Adriaensen, S., van Meer, H., De Meyer, K., Raynaud, C., Dehan, M., & Raskin, J.-P. (2003). Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Transactions on Electron Devices, 50(3), 577-588. https://doi.org/10.1106/TED.2003-810471 (Original work published 2003)