Potential and modelling of 1 mu m 1GHz SOI CMOS OTAs
(1997) Electronics Letters — Vol. 33, n° 9, p. 774-775 (1997)
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- Abstract
- High-frequency device models, design guidelines and frequency limitations are presented as well as layout and technology improvements to boost the transconductance at high frequency and to reduce the substrate capacitances. Implementations of one-stage and folded-cascode op-amps have been realised to validate the design method.
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Citations
Eggermont, J.-P., Flandre, D., Raskin, J.-P., & Colinge, J.-P. (1997). Potential and modelling of 1 mu m 1GHz SOI CMOS OTAs. Electronics Letters, 33(9), 774-775. https://doi.org/10.1049/el:19970517 (Original work published 1997)