Characterization and design methodology for low-distortion MOSFET-C analog structure's in multithreshold deep-submicrometer SOICMOS technologies

Vancaillie, L.;Flandre, Denis;Kilchytska, Valeriya;Alvarado, Joaquin;Cerdeira, A.
(2006) IEEE Transactions on Electron Devices — Vol. 53, n° 2, p. 263-269 (2006)

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The harmonic distortion (HD) of MOSFETs operating in the triode regime is thoroughly investigated for the different device types of a multi-V-th deep-submicrometer 0.12-mu m silicon-on-insulator (SOI) CMOS process. The measurements performed in a wide temperature range.(25 degrees C-220 degrees C) and on devices with different oxide thicknesses and channel dopings help to identify the relative impact of the different physical mechanisms at the origin of HD. A measurement-based and design-oriented methodology is finally developed to compare device types, biases and configurations responding to practical design targets.
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Vancaillie, L., Flandre, D., Kilchytska, V., Alvarado, J., & Cerdeira, A. (2006). Characterization and design methodology for low-distortion MOSFET-C analog structure’s in multithreshold deep-submicrometer SOICMOS technologies. IEEE Transactions on Electron Devices, 53(2), 263-269. https://doi.org/10.1109/TED.2005.861725 (Original work published 2006)