Influence of Gate Misalignment on the Electrical Characteristics of MuGFETs

Lee, Chi-Woo;Afzalian, Aryan;Dehdashti, Nima;Xiong, Weize;Colinge, Jean-Pierre
(2009) International Symposium on VLSI Technology – Systems and applications (VLSI-TSA) — Location: Hsinchu (Taiwan) (27.April.2009)

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Authors
  • Lee, Chi-WooTyndall National Institute, University of Cork
    Author
  • Afzalian, AryanUCLouvain
    Author
  • Dehdashti, NimaTyndall National Institute, University of Cork
    Author
  • Xiong, WeizeTexas Instruments Inc., dallas
    Author
  • Colinge, Jean-PierreTyndall National Institute, University of Cork
    Author
Abstract
This work studies the influence of gate misalignment on the electrical properties of MuGFETs using both measurements and 3D simulations. Electrical characteristics such as a DIBL, Vth and drain breakdown voltage are shown to be dependent on the gate misalignment due to the resulting change in fin width. Devices that have a Widening of the fin at the Drain side (DW) decreased due to weakening of gate control. Widening of the fin at the Source (SW), however, does not alter the device characteristics.
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Lee, C.-W., Afzalian, A., Dehdashti, N., Xiong, W., & Colinge, J.-P. (2009). Influence of Gate Misalignment on the Electrical Characteristics of MuGFETs. Proceedings of the International Symposium on VLSI Technology – Systems and applications (VLSI-TSA), p. 125-126. https://hdl.handle.net/2078.5/252476