Charge trapping phenomena in single electron NVM SOI devices fabricated by a self-aligned quantum dot technology
(2007) Nanoscaled semiconductor-on-insulator structures and devices — ISBN: [978-1-4020-6378-7], p. 251-256, published
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ChargeTrappingPhenomenainSingleElectronNVMSOIDevicesFabricatedbyaSelf-AlignedQuantumDotTechnology.pdf
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- Charge trapping in self-aligned single-dot memory devices fabricated by UCL technology based on arsenic-assisted etching and oxidation effects is investigated. The devices demonstrate room-temperature single-electron trapping in the Si nanodot floating gate circa 16 nm in size. The pulse transfer (Id - Vg) characteristics and time evolution of the drain current (Id - t) technique are employed for determination of the total charge storage in the Si nanodot floating gate and the gate-nanodot capacitance of the devices.
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Nazarov, A., Lysenko, V. S., Tang, X., Reckinger, N., & Bayot, V. (2007). Charge trapping phenomena in single electron NVM SOI devices fabricated by a self-aligned quantum dot technology. In Hall, S.; Nazarov, A.N.; Lysenko, V.S. (ed.), Nanoscaled semiconductor-on-insulator structures and devices (p. p. 251-256). Springer. https://hdl.handle.net/2078.5/201111