Compact and Efficient Encryption / Decryption Module for FPGA Implementation of AES
(2004) Embedded Cryptographic Hardware: Design and Security — ISBN: [1-59454-145-0], p. Part 1, Chapter 1, published
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- Authors
Legat, Jean-Didier 
- Abstract
- Hardware implementations of the Advanced Encryption Standard (AES) Rijndael algorithm have recently been the object of an intensive evaluation. Several papers describe effcient architectures for ASICs (Application Specific Integrated Circuits) and FPGAs (Field Programmable Gate Array). In this context, the highest effort was devoted to high throughput (up to 20 Gbps) encryption-only designs, fewer works studied low area encryption-only architectures and only a few papers have investigated low area encryption/decryption structures. However, in practice, only a few applications need throughput up to 20 Gbps while exible and low cost encryption/ decryption solutions are needed to protect sensible data, especially for embedded hardware applications. This contribution proposes an effcient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints. The proposed design into the smallest Xilinx FPGAs, deals with data streams of 208 Mbps, uses 163 slices and 3 RAM blocks and improves by 68% the best-known similar designs in terms of ratio Throughput=Area. We also propose implementations in other FPGA Families (Xilinx Virtex-II) and comparisons with similar DES, triple-DES and AES implementations.
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Citations
Rouvroy, G., Standaert, F.-X., Quisquater, J.-J., & Legat, J.-D. (2004). Compact and Efficient Encryption / Decryption Module for FPGA Implementation of AES. In Nadia Nedjah and Luiza de Macedo Mourelle (ed.), Embedded Cryptographic Hardware: Design and Security (p. p. Part 1, Chapter 1). Nova Science Publishers. https://hdl.handle.net/2078.5/253362