RF and linear performance of commercial 200 mm trap-rich HRSOI wafers for SoC applications
(2013) 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2013 — Location: Austin, Texas, USA (21.January.2013)
Files
SiRF2013trap-richRF.pdf
Restricted Access - Adobe PDF
- 212.87 KB
Details
- Authors
- Abstract
- We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than -81 dBm for a 900 MHz input signal with +15 dBm, i.e. more than 95 dBc. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of RF systems in Si.
- Affiliations
Citations
Roda Neve, C., Ben Ali, K., Malaquin, C., Allibert, F., Desbonnets, E., Bertrand, I., Van Den Daele, W., & Raskin, J.-P. (2013). RF and linear performance of commercial 200 mm trap-rich HRSOI wafers for SoC applications. SiRF 2013 Techn. Digest, pp. 15-17. https://hdl.handle.net/2078.5/230153