On-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory Computing
(2024) 2024 IEEE European Test Symposium (ETS) — Location: The Hague, Netherlands (20.May.2024)
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- Abstract
- In-memory computing (IMC) accelerators have become a pivotal architecture for enhancing AI algorithm computations, particularly critical for embedding deep neural networks (DNNs) in edge devices. The efficiency of these systems is paramount, yet IMC cores are prone to fluctuations due to process, temperature, and voltage variations, which can detrimentally impact DNN accuracy. This research introduces an innovative Built-In Self-Calibration (BISC) methodology, specifically designed to compensate for temperature-induced variations in mixed-signal IMC cores. The methodology enables real-time, on-chip adjustment of DNN weights during computation within the IMC core without modifying the computation path. The proposed approach, implemented on a silicon prototype, not only maintained DNN computation accuracy under substantial temperature variations but also fully compensated for almost 90% of the offset caused by these variations, without introducing any non-idealities.
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Citations
Singh, G., Numan, O., Monga, D., Andraud, M., & Halonen, K. (2024). On-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory Computing. 2024 IEEE European Test Symposium (ETS), The Hague, Netherlands. https://hdl.handle.net/2078.5/269968